Next: RSIM Version 1.0 License
Up: No Title
Previous: The unelf utility
References
- 1
-
James E. Bennett and Michael J. Flynn.
Performance Factors for Superscalar Processors.
Technical Report CSL-TR-95-661, Stanford University, February 1995.
- 2
-
Randy Brown.
Calendar Queues: A Fast O(1) Priority Queue
Implementation for the Simulation Event Set Problem.
Communications of the ACM, 31(10):1220-1227, October 1988.
- 3
-
R. G. Covington, S. Dwarkadas, J. R. Jump, S. Madala, and J. B. Sinclair.
The Efficient Simulation of Parallel Computer Systems.
International Journal of Computer Simulation, 1:31-58, January
1991.
- 4
-
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy.
Performance Evaluation of Memory Consistency Models for
Shared-Memory Multiprocessors.
In Proceedings of Fourth International Conference on
Architectural Support for Programming Languages and Operating Systems, pages
245-257, 1991.
- 5
-
Kourosh Gharachorloo, Anoop Gupta, and John Hennessy.
Two Techniques to Enhance the Performance of Memory
Consistency Models.
In Proceedings of the International Conference on Parallel
Processing, pages I355-I364, 1991.
- 6
-
Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip Gibbons, Anoop
Gupta, and John Hennessy.
Memory Consistency and Event Ordering in Scalable
Shared-Memory Multiprocessors.
In Proceedings of the 17th International Symposium on Computer
Architecture, pages 15-26, May 1990.
- 7
-
J. Robert Jump.
NETSIM Reference Manual.
Rice University Electrical and Computer Engineering Department, March
1993.
Available at http://www-ece.rice.edu/
rsim/rppt.html.
- 8
-
J. Robert Jump.
YACSIM Reference Manual.
Rice University Electrical and Computer Engineering Department, March
1993.
Available at http://www-ece.rice.edu/
rsim/rppt.html.
- 9
-
David R. Kaeli and Philip G. Emma.
Branch History Table Prediction of Moving Target Branches
Due to Subroutine Returns.
In Proceedings of the 18th Annual International Symposium on
Computer Architecture, pages 34-42, May 1991.
- 10
-
David Kroft.
Lockup-Free Instruction Fetch/Prefetch Cache
Organization.
In Proceedings of the 8th International Symposium on Computer
Architecture, pages 81-87, May 1981.
- 11
-
Leslie Lamport.
How to Make a Multiprocessor Computer That Correctly
Executes Multiprocess Programs.
IEEE Transactions on Computers, C-28(9):690-691, September
1979.
- 12
-
James Laudon and Daniel Lenoski.
The SGI Origin 2000: A ccNUMA Highly Scalable Server.
In Proceedings of the 24th International Symposium on Computer
Architecture, June 1997.
- 13
-
MIPS Technologies, Inc.
R10000 Microprocessor User's Manual, Version 2.0, December
1996.
- 14
-
Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve.
The Impact of Instruction Level Parallelism on
Multiprocessor Performance and Simulation Methodology.
In Proceedings of the 3rd International Symposium on High
Performance Computer Architecture, pages 72-83, February 1997.
- 15
-
Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton.
An Evaluation of Memory Consistency Models for
Shared-Memory Systems with ILP Processors.
In Proceedings of the 7th International Conference on
Architectural Support for Programming Languages and Operating Systems, pages
12-23, October 1996.
- 16
-
Parthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, and Sarita V. Adve.
The Interaction of Software Prefetching with ILP Processors
in Shared-Memory Systems.
In Proceedings of the 24th Annual International Symposium on
Computer Architecture, June 1997.
- 17
-
Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve.
Using Speculative Retirement and Larger Instruction
Windows to Narrow the Performance Gap between Memory Consistency
Models.
In Proceedings of the Ninth Annual ACM Symposium on Parallel
Algorithms and Architectures, June 1997.
- 18
-
Mendel Rosenblum, Edouard Bugnion, Stephen Alan Herrod, Emmet Witchel, and
Anoop Gupta.
The Impact of Architectural Trends on Operating System
Performance.
In Proceedings of the 15th ACM Symposium on Operating Systems
Principles, pages 285-298, December 1995.
- 19
-
Christoph Scheurich and Michel Dubois.
Correct Memory Operation of Cache-Based Multiprocessors.
In Proceedings 14th Annual International Symposium on Computer
Architecture, pages 234-243, Pittsburgh, PA, June 1987.
- 20
-
Jaswinder Pal Singh, Wolf-Dietrich Weber, and Anoop Gupta.
SPLASH: Stanford Parallel Applications for Shared-Memory.
Computer Architecture News, 20(1):5-44, March 1992.
- 21
-
Kevein Skadron and Douglas W. Clark.
Design Issues and Tradeoffs for Write Buffers.
In Proceedings of the 3rd International Symposium on High
Performance Computer Architecture, pages 144-155, February 1997.
- 22
-
J. E. Smith.
A study of branch prediction strategies.
In Proceedings of the 8th Annual Symposium on Computer
Architecture, pages 135-148, May 1981.
- 23
-
Sparc International.
The SPARC Architecture Manual, 1993.
Version 9.
- 24
-
Eric Sprangle, Robert S. Chappell, Mitch Alsup, and Yale N. Patt.
The Agree Predictor: A Mechanism for Reducing Negative
Branch History Interference.
In Proceedings of the 24th Annual International Symposium on
Computer Architecture, June 1997.
- 25
-
Sun Microelectronics.
UltraSPARC-II: Second Generation SPARC v9 64-Bit
Microprocessor With VIS, July 1997.
- 26
-
Sun Microsystems Inc.
The SPARC Architecture Manual, January 1991.
No. 800-199-12, Version 8.
- 27
-
Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and
Anoop Gupta.
The SPLASH-2 Programs: Characterization and Methodological
Considerations.
In Proceedings of the 22nd International Symposium on Computer
Architecture, pages 24-36, June 1995.
- 28
-
Kenneth C. Yeager.
The MIPS R10000 Superscalar Microprocessor.
IEEE Micro, 16(2):28-40, April 1996.
Vijay Sadananda Pai
Thu Aug 7 14:18:56 CDT 1997