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- memorylatency
- This number specifies the DRAM access latency in
cycles. (Note that this is only the actual time at the
DRAM, and does not include time on the bus, in the caches, or at any
other resource.) Defaults to 18 cycles (60 ns with a 300 MHz processor).
- dircycle
- This number gives the minimum directory access latency,
which is the latency incurred by non-data responses to the directory.
(Requests to the directory for data or data-carrying responses to the directory
must access the DRAM and thus incur the latency specified by memorylatency.)
This parameter is specified in processor cycles, and defaults to 3.
- meminterleaving
- This number specifies the degree of memory and
directory interleaving at each node. Defaults to 4.
- dirbufsize
- This number sets the maximum number of pending
requests at the directory at any time. If additional requests are
received, they are bounced back to the sender with a retry request.
- dirpacketcreate
- Some transactions require the directory to
send coherence requests to the other caches (such as invalidations
or cache-to-cache transfer requests). This number specifies the time
to produce the first such coherence request for a given transaction,
in processor cycles. Defaults to 12.
- dirpacketcreateaddtl
- This number specifies the additional
delay in processor cycles for each subsequent coherence request for a given
transaction (after the first one). Defaults to 6.
Vijay Sadananda Pai
Thu Aug 7 14:18:56 CDT 1997