The modules in the memory system are connected through ports, which are FIFO queues (see Section 12.1 for more information). Each port is a bidirectional connection, but the queues in each direction can have different lengths. An entry in the port queue is removed as soon as the appropriate module can start processing it. Thus, the port queue size also limits the number of requests that can be processed by the module each time the module is activated. For example, if a cache is intended to initiate processing for four requests each cycle, the request port queue should contain at least four entries.
The port queue can also contain more than the minimum number of entries; in these cases, the queue acts a buffer to decouple a faster module from a slower module. For this reason, the default port sizes from the L2 cache to the bus are larger than most of the other cache ports; these port sizes are chosen so that the potentially slow processing rate of the bus will not cause the L2 cache itself to stall.
The configurable port sizes are listed below, along with their default values. When applicable, the transaction type carried by each specified port is included in parentheses. These transaction types are explained in more detail in Section 12.2.
| Name | Description | Default |
| portszl1wbreq | L1  Write buffer (data request) | 2 |
| portszwbl1rep | Write buffer L1 (data reply) | 1 |
| portszwbl2req | Write buffer L2 (data request) | 1 |
| portszl2wbrep | L2 Write buffer (data reply) | 1 |
| portszl1l2req | L1 L2 (data request) | 1 |
| portszl2l1rep | L2 L1 (data reply) | 1 |
| portszl2l1cohe | L2 L1 (coherence request [including subset enforcement]) | 1 |
| portszl1l2cr | L1 L2 (coherence reply) | 1 |
| portszl2busreq | L2 Bus (data request) | 8 |
| portszl2buscr | L2 Bus (coherence reply, cache-to-cache data reply) | 8 |
| portszbusl2rep | Bus L2 (data reply) | 2 |
| portszbusl2cohe | Bus L2 (coherence request) | 2 |
| portszbusother | Bus other modules | 16 (per port) |
| portszdir | Directory bus | 64 (per port) |