Request header size (in bytes): (includes address, destination ID, source ID, command type, etc.)
Size of branch prediction table (unused if static): Number of shadow mappers: Return address stack size:
Number of functional units: ALU: FPU: Addr. gen.:
Number of register windows (including 1 reserved for system):
Functional unit latencies and repeat rates: The repeat delay if the number of cycles before a functional unit is ready to start processing a new input (the inverse of the repeat rate).
Cache line size:
L1 cache size (in KB): L1 set associativity: Number of L1 cache request ports: L1 cache access latency (in processor cycles):
L2 cache size (in KB): L2 set associativity: L2 cache tag array access latency (in processor cycles): L2 cache data array access latency (in processor cycles): Extra write-back buffer entries:
Cache coherence protocol: MESI MSI
Write buffer size (used only with write-through L1 cache):
Limit on number of coalesced requests in an MSHR:
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