Source files: src/MemSys/l1cache.c, src/MemSys/l2cache.c, src/MemSys/pipeline.c
Header files: incl/MemSys/cache.h, incl/MemSys/pipeline.h
Two functions are used to bring new messages into each level of cache. These functions are L1CacheInSim and L2CacheInSim. Each of these functions checks incoming messages from the ports of the module. The function then attempts to insert each incoming message into the appropriate tag-array pipeline, according to its s.type field. If the message can be added to its pipeline, it is removed from its input port; otherwise, it remains on the input port for processing in a future cycle.
At the L2 cache, if the incoming message is a REPLY, then some bookkeeping is done for managing the write-back buffer. Specifically, before a REQUEST can be sent out from the L2 cache, it must have allocated a write-back buffer entry for a potential replacement caused by its REPLY. When the REPLY returns to the cache, the wrb_buf_used field of the cache is incremented to indicate that the new REPLY may need to send out a replacement.