Overall system parameters

Number of nodes in system:

Request header size (in bytes):
(includes address, destination ID, source ID, command type, etc.)

Processor parameters

Branch predictor type:
2-bit history
2-bit agree
static

Size of branch prediction table (unused if static):
Number of shadow mappers:
Return address stack size:

Number of functional units: ALU: FPU: Addr. gen.:

Number of register windows (including 1 reserved for system):

Functional unit latencies and repeat rates:
The repeat delay if the number of cycles before a functional unit is ready to start processing a new input (the inverse of the repeat rate).
DescriptionLatencyRepeat delay
Common ALU operations
Integer multiply
Integer divide
Integer shift
Common FPU operations
FPU move/abs/neg
FPU conversions
FPU divide
FPU square root
Maximum stack size per process (in KB):

Cache hierarchy parameters

L1 cache type:
write-through, no-write-allocate
write-back, write-allocate

Cache line size:

L1 cache size (in KB):
L1 set associativity:
Number of L1 cache request ports:
L1 cache access latency (in processor cycles):

L2 cache size (in KB):
L2 set associativity:
L2 cache tag array access latency (in processor cycles):
L2 cache data array access latency (in processor cycles):
Extra write-back buffer entries:

Cache coherence protocol:
MESI
MSI

Write buffer size (used only with write-through L1 cache):

Limit on number of coalesced requests in an MSHR:

Bus parameters

Bus width (in bytes):
Bus cycle time (in processor cycles):
Bus arbitration delay (in processor cycles):

Directory and memory parameters

DRAM access latency (not counting bus or cache delays; in processor cycles):
Minimum directory access latency (for non-data responses; in processor cycles):
Degree of directory/memory interleaving per node:
Directory pending request buffer size:
Directory coherence packet creation time, initial (in processor cycles):
Directory coherence packet creation time, subsequent (in processor cycles):

Interconnection network parameters

Network flit size (in bytes):
Flit delay at network switches (in processor cycles):
Arbitration delay at network multiplexers (in processor cycles):
Granularity of switch pipelining (in processor cycles; 0 means non-pipelined):
Switch buffer size (in flits):
Port buffer size (in packets):

Queue sizes connecting various modules

These queues are described in greater detail in the manual. The entries here represent the number of messages that can be held in each queue at a time. Note that an entry in a port queue is removed as soon as the appropriate module can start processing it. Thus, if the module can start processing new transactions every cycle (as the caches and write-buffer do in the absence of contention), the number of entries represents the maximum number of new transactions of that type for a given cycle (if the module itself can support that many).

DescriptionValue
L1 to Write buffer (REQ)
Write buffer to L1 (REPLY)
Write buffer to L2 (REQ)
L2 to Write buffer(REPLY)
L1 to L2 (REQ)
L2 to L1 (REPLY)
L2 to L1 (COHE)
L1 to L2 (COHE_REPLY)
L2 to Bus (REQ)
Bus to L2 (REPLY)
Bus to L2 (COHE)
L2 to Bus (COHE_REPLY/REPLY)
Bus to other modules (per port)
Directory to Bus (per port)
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