Alberto Ros

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I am Full Professor in the Computer Engineering Department at the University of Murcia, Spain. Funded by the Spanish government to conduct the PhD studies I received the PhD in computer science from the University of Murcia in 2009. I held postdoctoral positions at the Technical University of Valencia and at Uppsala University. I received an European Research Council (ERC) Consolidator Grant in 2018 to improve the performance of multicore architectures. Working on cache coherence, memory hierarchy designs, memory consistency, and processor microarchitecture, I have co-authored more than 100 peer-reviewed articles. I have been inducted into the ISCA Hall of Fame and MICRO Hall of Fame. I am IEEE Senior member.

Alberto Ros' DBLP Bibliography Server

Alberto Ros' Google Scholar Citations

Most relevant publications sorted by year, publication type, or topic

2024

• Sebastian S. Kim, Alberto Ros, "Effective Context-Sensitive Memory Dependence Prediction". 30th Symposium on High Performance Computer Architecture (HPCA), pages 515--527, Edinburgh, Scotland, March 2024. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "Wrong-Path-Aware Entangling Instruction Prefetcher". IEEE Transactions on Computers (TC), vol. 73 (2), pages 548--559, February 2024. [PDF] [BibTeX entry]
• Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "On the Interactions between ILP and TLP with Hardware Transactional Memory". Microprocessors and Microsystems (MICPRO), vol. 104, pages 104975, February 2024. [PDF] [BibTeX entry]

2023

• Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros, "CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions". 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 1--13, Vienna, Austria, October 2023. [PDF] [BibTeX entry]
• Josué Feliu, Arthur Perais, Daniel Jimenez, Alberto Ros, "Rebasing Microarchitectural Research with Industry Traces". 2023 IEEE International Symposium on Workload Characterization (IISWC), pages 100--114, Ghent, Belgium, October 2023. [PDF] [BibTeX entry]
• Emilio Dominguez-Sanchez, Alberto Ros, "MBPlib: Modular Branch Prediction Library". International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 71--80, Raleigh, NC (USA), April 2023. [PDF] [BibTeX entry]
• Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras, "Speculative Inter-Thread Store-to-Load Forwarding in SMT Architectures". Journal of Parallel Distributed Computing (JPDC), vol. 173, pages 94--106, March 2023. [PDF] [BibTeX entry]
• Bhargavi R. Upadhyay, Alberto Ros, Supriya M., "Fine-Grain Data Classification to Filter Token Coherence Traffic". Journal of Parallel Distributed Computing (JPDC), vol. 171, pages 40--53, January 2023. [PDF] [BibTeX entry]

2022

• Eduardo José Gómez-Hernández, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Splash-4: A Modern Benchmark Suite with Lock-Free Constructs". 2022 IEEE International Symposium on Workload Characterization (IISWC), pages 51--64, Austin, TX (USA), November 2022. [PDF] [BibTeX entry]
• Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul Gratz, Daniel Jimenez, Samira Mirbagher-Ajorpaz, "Composite Instruction Prefetching: Combining Complementary Instruction Prefetchers". 40th IEEE International Conference on Computer Design (ICCD), pages 471--478, Lake Tahoe, NV (USA), October 2022. [PDF] [BibTeX entry]
• Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, V. Viñals-Yúfera, Alberto Ros, "Berti: An Accurate Local-Delta Data Prefetcher". 55th International Symposium on Microarchitecture (MICRO), pages 975--991, Chicago, IL (USA), October 2022. [PDF] [BibTeX entry]
• Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros, "Exploring Instruction Fusion Opportunities in General Purpose Processors". 55th International Symposium on Microarchitecture (MICRO), pages 199--212, Chicago, IL (USA), October 2022. [PDF] [BibTeX entry]
• Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros, "Free Atomics: Hardware Atomic Operations without Fences". 49th International Symposium on Computer Architecture (ISCA), pages 14--26, New York, NY (USA), June 2022. [PDF] [BibTeX entry]
• Juan Manuel Cebrian, Thibaud Balem, Adrian Barredo, Marc Casas, Miquel Moreto, Alberto Ros, Alexandra Jimborean, "Compiler-Assisted Compaction/Restoration of SIMD Instructions". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33 (4), pages 779--791, April 2022. [PDF] [BibTeX entry]
• Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory". 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pages 157--164, Worldwide event, March 2022. [PDF] [BibTeX entry]
• Marina Shimchenko, Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, "Analysing Software Prefetching Opportunities in Hardware Transactional Memory". Journal of Supercomputing (SUPE), vol. 78 (1), pages 919--944, January 2022. [PDF] [BibTeX entry]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros, "DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 33 (1), pages 1--13, January 2022. [PDF] [BibTeX entry]

2021

• Bhargavi R. Upadhyay, Alberto Ros, Jalpa Shah, "Efficient Classification of Private Memory Blocks". Journal of Parallel Distributed Computing (JPDC), vol. 157, pages 256--268, November 2021. [PDF] [BibTeX entry]
• Eduardo José Gómez-Hernández, Rubén Titos-Gil, Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations". 54th International Symposium on Microarchitecture (MICRO), pages 337--349, Worldwide event, October 2021. [PDF] [BibTeX entry]
• Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras, "ITSLF: Inter-Thread Store-to-Load Forwarding in Simultaneous Multithreading". 54th International Symposium on Microarchitecture (MICRO), pages 1296--1308, Worldwide event, October 2021. [PDF] [BibTeX entry]
• Christos Sakalis, Zamshed Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu, "Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation". 1st IEEE International Symposium on Secure and Private Execution Environment Design (SEED), pages 89--100, Worldwide event, September 2021. [PDF] [BibTeX entry]
• Alberto Ros, "BL∪E: A Timely, IP-based Data Prefetcher". The 1st ML-Based Data Prefetching Competition. ML for Computer Architecture and Systems, Worldwide event, June 2021. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "A Cost-Effective Entangling Prefetcher for Instructions". 48th International Symposium on Computer Architecture (ISCA), pages 99--111, Worldwide event, June 2021. [PDF] [BibTeX entry]
• Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros, "Splash-4: Improving Scalability with Lock-Free Constructs". International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 235--236, Worldwide event, March 2021. [PDF] [BibTeX entry]
• Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras, "TSOPER: Efficient Coherence-Based Strict Persistency". 12th Non-Volatile Memories Workshop (NVMW'21), University of California, San Diego, March 2021. [PDF] [BibTeX entry]
• Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras, "TSOPER: Efficient Coherence-Based Strict Persistency". 27th Symposium on High Performance Computer Architecture (HPCA), pages 125--138, Worldwide event, February 2021. [PDF] [BibTeX entry]

2020

• Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander, "Understanding Selective Delay as a Method for Efficient Secure Speculative Execution". IEEE Transactions on Computers (TC), vol. 69 (11), pages 1584--1595, November 2020. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Speculative Enforcement of Store Atomicity". 53rd International Symposium on Microarchitecture (MICRO), pages 555--567, Worldwide event, October 2020. [PDF] [BibTeX entry]
• Juan Manuel Cebrian, Stefanos Kaxiras, Alberto Ros, "Boosting Store Buffer Efficiency with Store-Prefetch Bursts". 53rd International Symposium on Microarchitecture (MICRO), pages 568--580, Worldwide event, October 2020. [PDF] [BibTeX entry]
• Sawan Singh, Alexandra Jimborean, Alberto Ros, "Regional Out-of-Order Writes in Total Store Order". 29th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 205--216, Worldwide event, October 2020. [PDF] [BibTeX entry]
• Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean, "Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design". 29th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 241--254, Worldwide event, October 2020. [PDF] [BibTeX entry]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "PfTouch: Concurrent Page-Fault Handling for Intel Restricted Transactional Memory". Journal of Parallel Distributed Computing (JPDC), vol. 145, pages 111--123, November 2020. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "The Entangling Instruction Prefetcher". IEEE Computer Architecture Letters (CAL), vol. 19 (2), pages 84--87, July 2020. [PDF] [BibTeX entry]
• Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Concurrent Irrevocability in Best-Effort Hardware Transactional Memory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 31 (6), pages 1301--1315, June 2020. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "The Entangling Instruction Prefetcher". The 1st Instruction Prefetching Championship, Worldwide event, May 2020. [PDF] [BibTeX entry]
• Bhargavi R. Upadhyay, Alberto Ros, Murty NS, "TLB-based Block-Grain Classification of Private Data". 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), pages 122--130, Vasteras, Sweden, March 2020. [PDF] [BibTeX entry]

2019

• Rubén Titos-Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio, "Way Combination for an Adaptive and Scalable Coherence Directory". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 30 (11), pages 2608--2623, November 2019. [PDF] [BibTeX entry]
• Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander, "Efficient Invisible Speculative Execution through Selective Delay and Value Prediction". 46th International Symposium on Computer Architecture (ISCA), pages 723--735, Phoenix, AZ (USA), June 2019. [PDF] [BibTeX entry]
• Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras, "Filter Caching for Free: The Untapped Potential of the Store Buffer". 46th International Symposium on Computer Architecture (ISCA), pages 436--448, Phoenix, AZ (USA), June 2019. [PDF] [BibTeX entry]
• Alberto Ros, "Berti: A Per-Page Best-Request-Time Delta Prefetcher". The 3rd Data Prefetching Championship, Phoenix, AZ (USA), June 2019. [PDF] [BibTeX entry]
• Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander, "Ghost Loads: What is the Cost of Invisible Speculation?". ACM International Conference on Computing Frontiers, pages 153--163, Alghero, Sardinia, Italy, April 2019. [PDF] [BibTeX entry]

2018

• Alberto Ros, Stefanos Kaxiras, "The Superfluous Load Queue". 51st International Symposium on Microarchitecture (MICRO), pages 95--107, Fukuoka, Japan, October 2018. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Non-Speculative Store Coalescing in Total Store Order". 45th International Symposium on Computer Architecture (ISCA), pages 221--234, Los Angeles, CA (USA), June 2018. [PDF] [BibTeX entry]
• Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros, "Non-Speculative Load Reordering in TSO". IEEE Micro (TopPicks), vol. 38 (3), pages 48--57, May 2018. [PDF] [BibTeX entry]
• Albert Esteve, Alberto Ros, Antonio Robles, María E. Gómez, "TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 29 (5), pages 1188--1201, May 2018. [PDF] [BibTeX entry]
• Alexandra Jimborean, Per Ekemark, Jonatan Waern, Stefanos Kaxiras, Alberto Ros, "Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 29 (3), pages 527--541, March 2018. [PDF] [BibTeX entry]
• José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio, "Photonic-Based Express Coherence Notications for Many-core CMPs". Journal of Parallel Distributed Computing (JPDC), vol. 113, pages 179--194, March 2018. [PDF] [BibTeX entry]
• Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu, "Mending Fences with Self-Invalidation and Self-Downgrade". Logical Methods in Computer Science (LMCS), vol. 14 (1), pages 1--33, January 2018. [PDF] [BibTeX entry]

2017

• Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras, "Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28 (12), pages 3413--3425, December 2017. [PDF] [BibTeX entry]
• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "To Be Silent or Not: On the Impact of Evictions of Clean Data in Cache-Coherent Multicores". Journal of Supercomputing (SUPE), vol. 73 (10), pages 4428--4443, October 2017. [PDF] [BibTeX entry]
• Albert Esteve, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28 (8), pages 2401--2413, August 2017. [PDF] [BibTeX entry]
• Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras, "Non-Speculative Load-Load Reordering in TSO". 44th International Symposium on Computer Architecture (ISCA), pages 187--200, Toronto, ON (Canada), June 2017. [PDF] [BibTeX entry]
• Rubén Titos-Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Way-Combining Directory: An Adaptive and Scalable Low-Cost Coherence Directory". International Conference on Supercomputing (ICS), pages 20:1--20:10, Chicago, IL (USA), June 2017. [PDF] [BibTeX entry]
• Alexandra Jimborean, Jonatan Waern, Per Ekemark, Stefanos Kaxiras, Alberto Ros, "Automatic Detection of Extended Data-Race-Free Regions". 15th International Symposium on Code Generation and Optimization (CGO), pages 14--26, Austin, TX (USA), February 2017. [PDF] [BibTeX entry]
• Joan J. Valls, Alberto Ros, María E. Gómez, Julio Sahuquillo, "The Tag Filter Architecture: An Energy-Efficient Cache and Directory Design". Journal of Parallel Distributed Computing (JPDC), vol. 100 (2), pages 193--202, February 2017. [PDF] [BibTeX entry]
• Juan M. Cebrian, Ricardo Fernández-Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros, "A Dedicated Private-Shared Cache Design for Scalable Multiprocessors". Concurrency and Computation: Practice and Experience (CPE), vol. 29 (2), January 2017. [PDF] [BibTeX entry]

2016

• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "A Directory Cache with Dynamic Private-Shared Partitioning". 23rd International Conference on High Performance Computing (HiPC), pages 382--391, Hyderabad (India), December 2016. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Racer: TSO Consistency via Race Detection". 49th International Symposium on Microarchitecture (MICRO), pages 1--13, Taipei, Taiwan, October 2016. [PDF] [BibTeX entry]
• Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras, "POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics". 25th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 433--434, Haifa (Israel), September 2016. [PDF] [BibTeX entry]
• Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu, "Fencing Programs with Self-Invalidation and Self-Downgrade". International Conference, FORTE 2016, Held as Part of the 11th International Federated Conference on Distributed Computing Techniques, DisCoTec 2016, pages 19--35, Heraklion (Crete), June 2016. [PDF] [BibTeX entry]
• Albert Esteve, Alberto Ros, Antonio Robles, María E. Gómez, José Duato, "TokenTLB: A Token-Based Page Classification Approach". International Conference on Supercomputing (ICS), pages 26:1--26:13, Istanbul (Turkey), June 2016. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27 (11), pages 3101--3115, November 2016. [PDF] [BibTeX entry]
• Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, Alberto Ros, "Splash-3: A Properly Synchronized Benchmark Suite for Contemporary Research". International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 101--111, Uppsala (Sweden), April 2016. [PDF] [BibTeX entry]
• Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead". ACM Transactions on Architecture and Code Optimization (TACO), vol. 13 (1), pages 1:1--1:22, March 2016. [PDF] [BibTeX entry]
• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence". International Conference on Architecture of Computing Systems (ARCS), pages 100--112, Nuremberg (Germany), April 2016. [PDF] [BibTeX entry]
• Albert Esteve, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27 (3), pages 748--761, March 2016. [PDF] [BibTeX entry]
• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Are Distributed Sharing Codes a Solution to the Scalability Problem of Coherence Directories in Manycores? An Evaluation Study". Journal of Supercomputing (SUPE), vol. 72 (2), pages 612--638, February 2016. [PDF] [BibTeX entry]

2015

• Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "An Efficient, Self-Contained, On-Chip, Directory: DIR1-SISD". 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 317--330, San Francisco, CA (USA), October 2015. [PDF] [BibTeX entry]
• Juan M. Cebrian, Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, "Early Experiences with Separate Caches for Private and Shared Data". 1st Workshop on E-science ReseaRch leading tO negative Results (ERROR), pages 572--579, Munich (Germany), September 2015. [PDF] [BibTeX entry]
• Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras, "The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence". ACM Transactions on Architecture and Code Optimization (TACO), vol. 12 (3), pages 26:1--26:21, August 2015. [PDF] [BibTeX entry]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS Directory: A Scalable Multilevel Directory Cache for CMPs". Journal of Supercomputing (SUPE), vol. 71 (8), pages 2847--2876, August 2015. [PDF] [BibTeX entry]
• Stefanos Kaxiras, David Klaftenegger, Magnus Norgren, Alberto Ros, Konstantinos Sagonas, "Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory". 24th International Symposium on High-Performance Parallel and Distributed Computing (HPDC), pages 3--14, Portland, OR (USA), June 2015. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Callback: Efficient Synchronization without Invalidation with a Directory Just for Spin-Waiting". 42nd International Symposium on Computer Architecture (ISCA), pages 427--438, Portland, OR (USA), June 2015. [PDF] [BibTeX entry]
• Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García, "Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses". IEEE Transactions on Computers (TC), vol. 64 (6), pages 1534--1547, June 2015. [PDF] [BibTeX entry]
• Alberto Ros, Alexandra Jimborean, "A Dual-Consistency Cache Coherence Protocol". 29th International Parallel & Distributed Processing Symposium (IPDPS), pages 1119--1128, Hyderabad (India), May 2015. [PDF] [BibTeX entry]
• Joan J. Valls, Julio Sahuquillo, Alberto Ros, María E. Gómez, "The Tag Filter Cache: An Energy-Efficient Approach". 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pages 182--189, Turku (Finland), March 2015. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, "DASC-DIR: A Low-Overhead Coherence Directory for Many-Core Processors". Journal of Supercomputing (SUPE), vol. 71 (3), pages 781--807, March 2015. [PDF] [BibTeX entry]
• Alberto Ros, Mahdad Davari, Stefanos Kaxiras, "Hierarchical Private/Shared Classification: the Key to Simple and Efficient Coherence for Clustered Cache Hierarchies". 21st Symposium on High Performance Computer Architecture (HPCA), pages 186--197, Bay area, CA (USA), February 2015. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Fast&Furious: A Tool for Detecting Covert Racing". 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA) and 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms (DITAM), pages 1--6, Amsterdam (The Netherlands), January 2015. [PDF] [BibTeX entry]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS-Cache: An Energy-Efficient Cache Design for Chip Multiprocessors". Journal of Supercomputing (SUPE), vol. 71 (1), pages 67--86, January 2015. [PDF] [BibTeX entry]

2014

• Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio, "Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs". 3rd Workshop on On-Chip Memory Hierarchies and Interconnects (OMHI), pages 254--265, Porto (Portugal), August 2014. [PDF] [BibTeX entry]

2013

• Alberto Ros, Blas Cuesta, María E. Gómez, Antonio Robles, José Duato, "Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors". 42nd International Conference on Parallel Processing (ICPP), pages 562--571, Lyon (France), October 2013. [PDF] [BibTeX entry]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, "PS-Cache: An Energy-Efficient Cache Design for Chip Multiprocessors". 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 407, Edinburgh (Scotland), September 2013. [PDF] [BibTeX entry]
• José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio, "ECONO: Express Coherence Notifications for Efficient Cache Coherency in Many-Core CMPs". XIII International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pages 237--244, Samos (Greece), July 2013. [PDF] [BibTeX entry]
• Stefanos Kaxiras, Alberto Ros, "A New Perspective for Efficient Virtual-Cache Coherence". 40th International Symposium on Computer Architecture (ISCA), pages 535--547, Tel-Aviv (Israel), June 2013. [PDF] [BibTeX entry]
• José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio, "Efficient Dir0B Cache Coherency for Many-Core CMPs". 18th International Conference on Computational Science (ICCS), pages 2545--2548, Barcelona (Spain), June 2013. [BibTeX entry]
• Blas Cuesta, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Non-Coherent Memory Blocks". IEEE Transactions on Computers (TC), vol. 62 (3), pages 482--495, March 2013. [PDF] [BibTeX entry]

2012

• Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, "Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs". 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 43--50, Columbia University, NY (USA), October 2012. [PDF] [BibTeX entry]
• Alberto Ros, Stefanos Kaxiras, "Complexity-Effective Multicore Coherence". 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 241--252, Minneapolis, MN (USA), September 2012. [PDF] [BibTeX entry]
• Joan J. Valls, Alberto Ros, Julio Sahuquillo, María E. Gómez, José Duato, "PS-Dir: A Scalable Two-Level Directory Cache". 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 451--452, Minneapolis, MN (USA), September 2012. [PDF] [BibTeX entry]
• Stefanos Kaxiras, Alberto Ros, "Efficient, Snoopless, System-on-Chip Coherence". 25th IEEE International System-on-Chip Conference (IEEE SOCC), pages 230--235, Niagara Falls, NY (USA), September 2012. [PDF] [BibTeX entry]
• Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García, "ASCIB: Adaptive Selection of Cache Indexing Bits for Reducing Conflict Misses". International Symposium on Low Power Electronics and Design (ISLPED), pages 51--56, Redondo Beach, CA (USA), July 2012. [PDF] [BibTeX entry]
• Alberto Ros, Blas Cuesta, María E. Gómez, Antonio Robles, José Duato, "Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems". 4th International Workshop on Multicore and Multithreaded Architectures and Algorithms (M2A2), pages 691--696, Madrid (Spain), July 2012. [PDF] [BibTeX entry]
• Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, Maria E. Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato, "Extending Magny-Cours Cache Coherence". IEEE Transactions on Computers (TC), vol. 61 (5), pages 593--606, May 2012. [PDF] [BibTeX entry]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "DAPSCO: Distance-Aware Partially Shared Cache Organization". ACM Transactions on Architecture and Code Optimization (TACO), vol. 8 (4), pages 25:1--25:19, January 2012. [PDF] [BibTeX entry]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "DAPSCO: Distance-Aware Partially Shared Cache Organization". 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), pages 25:1--25:19, Paris (France), January 2012. [PDF] [BibTeX entry]

2011

• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation". 40th International Conference on Parallel Processing (ICPP), pages 51--62, Taipei (Taiwan), September 2011. [PDF] [BibTeX entry]
• Francisco Triviño, Francisco J. Andujar, José L. Sánchez, Francisco J. Alfaro, Alberto Ros, "Self-Related Traces: An Alternative to Full-System Simulation for Networks-On-Chip". International Conference on High Performance Computing & Simulation (HPCS), pages 819--824, Istanbul (Turkey), July 2011. [PDF] [BibTeX entry]
• Blas Cuesta, Alberto Ros, María E. Gómez, Antonio Robles, José Duato, "Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks". 38th International Symposium on Computer Architecture (ISCA), pages 93--103, San Jose, CA (USA), June 2011. [PDF] [BibTeX entry]

2010

• Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, María E. Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato, "EMC²: Extending Magny-Cours Coherence for Large-Scale Servers". 17th International Conference on High Performance Computing (HiPC), pages 1--10, Goa (India), December 2010. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, "A Direct Coherence Protocol for Many-Core Chip Multiprocessors". IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 21 (12), pages 1779--1792, December 2010. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, "Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs". 4th Workshop on Highly Parallel Processing on a Chip (HPPC), pages 87--97, Ischia (Italy), August 2010. [PDF] [BibTeX entry]
• Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García, "Exploring the Field of Cache Coherence Protocols For Server Consolidation". 6th HiPEAC Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), pages 211--214, Terrasa (Spain), July 2010. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, "A Scalable Organization for Distributed Directories". Journal of Systems Architecture (JSA), vol. 56 (2-3), pages 77--87, March 2010. [PDF] [BibTeX entry]
• Alberto Ros, "Efficient and Scalable Cache Coherence for Chip Multiprocessors: Novel Proposals for Managing Cache Coherence in Future Many-Core Chip Multiprocessors", LAP Lambert Academic Publishing, February 2010. [url] [BibTeX entry]
• Alberto Ros, "Parallel and Distributing Computing", IN-TECH, January 2010. [url] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, Cache Coherence Protocols for Many-Core CMPs, "Parallel and Distributing Computing", IN-TECH, pages 93--118, January 2010. [PDF] [BibTeX entry]

2009

• Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García, "Distance-Aware Round-Robin Mapping for Large NUCA Caches". 16th International Conference on High Performance Computing (HiPC), pages 79--88, Kochi (India), December 2009. [PDF] [BibTeX entry]
• Alberto Ros, "Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors". Universidad de Murcia. Advisor: José Manuel García, Manuel Eugenio Acacio, September 2009. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, "Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs". 8th International Conference on Advanced Parallel Processing Technologies (APPT), pages 11--27, Rapperswil (Switzerland), August 2009. [PDF] [BibTeX entry]

2008

• Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García, "Two Proposals for the Inclusion of Directory Information in the Last-Level Private Caches of Glueless Shared-Memory Multiprocessors". Journal of Parallel Distributed Computing (JPDC), vol. 68 (11), pages 1413--1424, November 2008. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, "Scalable Directory Organization for Tiled CMP Architectures". International Conference on Computer Design (CDES), pages 112--118, Las Vegas, NV (USA), July 2008. [PDF] [BibTeX entry]
• Alberto Ros, Manuel E. Acacio, José M. García, "DiCo-CMP: Efficient Cache Coherency in Tiled CMP Architectures". 22nd International Parallel & Distributed Processing Symposium (IPDPS), pages 1--11, Miami, FL (USA), April 2008. [PDF] [BibTeX entry]

2007

• Alberto Ros, Manuel E. Acacio, José M. García, "Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors". 14th International Conference on High Performance Computing (HiPC), pages 147--160, Goa (India), December 2007. [PDF] [BibTeX entry]

2006

• Alberto Ros, Manuel E. Acacio, José M. García, "An Efficient Cache Design for Scalable Glueless Shared-Memory Multiprocessors". ACM International Conference on Computing Frontiers, pages 321--330, Ischia (Italy), May 2006. [PDF] [BibTeX entry]

2005

• Alberto Ros, Manuel E. Acacio, José M. García, "A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors". 11th International Euro-Par Conference, pages 582--591, Lisbon (Portugal), August 2005. [PDF] [BibTeX entry]

2004

• Alberto Ros, "Diseño y Evaluación de una Arquitectura basada en Directorio Ligero". Universidad de Murcia. Advisor: José Manuel García, Manuel Eugenio Acacio, July 2004. [BibTeX entry]