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I am an assistant professor at the Department of Computer Engineering, University of Murcia. My research interests include everything related to the architectural design of multiprocessors, with particular interest in the hardware support for transactional memory. My main objective is to improve synchronization in parallel programs to enable easier-to-program yet efficient parallel applications that can take advantage of current and future multicore computers. Since returning to my alma mater in 2016, I have taugth various undegraduate courses on Computer Organization, Computer Networks and Operating Systems.

Short Bio


I started my research career in 2006, after I received BS and MS degrees in Computer Science from the University of Murcia. In 2007, I was one of the recipients of the FPU scholarships (Formación de Profesorado Universitario) granted by the Spanish Ministry of Education and Science. I received a PhD degree from the University of Murcia in 2011, with a thesis entitled Hardware techniques for high-performance transactional Memory in many-core chip multiprocessors, advised by  Prof. Manuel Acacio and Prof. José M. García.

I held postdoctoral positions at Chalmers University of Technology (2012-2014) and Barcelona Supercomputing Center (2014-2015). During my time with the Computer Architecture for Parallel Paradigms Group at BSC I was involved in the ParaDIME project, where my research was focused on architectural support for efficient message passing. While at the Department of Computer Science and Engineering @ Chalmers, I worked with Prof. Per Stenström on the SSF-founded project Software Abstractions for Heterogeneous Multicore Systems, and I was also in charge of the quarterly newsletter of the HiPEAC Network of Excellence.

Contact

Rubén Titos Gil
Departamento de Ingeniería y Tecnología de Computadores
Facultad de Informática
Campus de Espinardo
30100 Murcia (SPAIN)

e-mail: rtitos [at] um [dot] es
Phone: +34 868 888510
Fax: +34 868 884151
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