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Overview of RSIM Implementation
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RSIM DEVELOPER'S GUIDE
Overview of RSIM Implementation
Event-driven Simulation Library
Event-manipulation functions
Semaphore functions
Memory allocation functions
Initialization and Configuration Routines in RSIM
RSIM_EVENT
and the Out-of-order Execution Engine
Overview of
RSIM_EVENT
Instruction fetch and decode
Branch prediction
Instruction issue
Instruction execution
Completion
Graduation
Exception handling
Principal data structures
Processor Memory Unit
Adding new instructions to the memory unit
Address generation
Issuing instructions to the memory hierarchy
Completing memory instructions in the memory hierarchy
Memory Hierarchy and Interconnection System Fundamentals
Fundamentals of memory system modules
Memory system message data structure
The
s.type
field
The
req_type
field
The
s.reply
field
The
s.nack_st
field
Memory system simulator initialization
Deadlock avoidance
Cache Hierarchy
Bringing in messages
Processing the cache pipelines
Processing L1 cache actions
Handling
REQUEST
type
Handling
REPLY
type
Handling
COHE
type
Processing L2 tag array accesses
Processing L2 data array accesses
Cache initialization and statistics
Discussion of cache coherence protocol implementation
Coalescing write buffer
Deadlock avoidance
Directory and Memory Simulation
Obtaining a new or incomplete transaction to process
Processing incoming
REQUEST
s
Sending out
COHE
messages
Processing incoming write-back and replacement messages
Processing other incoming
COHE_REPLY
s
Handling positive acknowledgments
Handling negative acknowledgments
Deadlock avoidance
System Interconnects
Node bus
Network interface modules
Multiprocessor interconnection network
Deadlock avoidance
Statistics and Debugging Support
Statistics
Debugging Support
Implementation of
predecode
and
unelf
The
predecode
utility
The
unelf
utility
Vijay Sadananda Pai
Thu Aug 7 14:18:56 CDT 1997