Memory unit parameters

-m num

Maximum number of operations in the processor memory unit, described in Section 3.2.3. Defaults to 32.

-L num

Represents the memory ordering constraint for uniprocessor data dependences in the situation of a load past a prior store with an unknown address (as described in Section 3.2.3). The following table specifies the policies supported:

Policy number Description

0 Stall load until all previous store addresses known (supported only with release consistency)

1 Issue load, but do not let other instructions use load value until & all previous store addresses known (supported only with release consistency)

2 Issue load and let other instructions use load value even when addresses of previous stores are unknown. & If prior store later discovered to have conflicting address, & cause soft exception. This is the default.

-p

Turn on hardware-controlled prefetching for optimized consistency implementations (discussed in Section 3.2.3). Bring all hardware prefetches to L1 cache.

-P

Same as ``-p'', but brings write prefetches only to L2 cache.

-J

All prefetches (software and hardware) go only to L2 cache.

-K

Enable speculative load execution for optimized consistency implementations (discussed in Section 3.2.3).

-N

Store buffering in SC: allows stores to graduate before completion [4, 17] (useful in SC only; stores graduate before completion in all other models by default; discussed in Section 3.2.3)

-6

Processor consistency, if RSIM compiled with -DSTORE_ORDERING. RSIM compiled with -DSTORE_ORDERING provides SC by default.