These parameters allow RSIM to simulate simple processors with single instruction issue, static scheduling, and blocking reads, possibly with increased processor and/or cache clock rates. These parameters were used in our previous work to investigate the effectiveness of models based on simple processors in approximating the behavior of ILP processors [14]. It is important to note that the change in processor speed brought about by these parameters do not affect the latencies in absolute times for the other modules. For example, if the DRAM memory latency is specified to be 18 processor cycles with the default processor speed of 300 MHz, this translates to a 60 ns access time. With the ``-F4'' option, which speeds up the processor by a factor of 4, RSIM automatically increases the DRAM speed in terms of processor cycles by a factor of 4 (i.e. 72 processor cycles and 60 ns in absolute time).
These approximate simulation models are not intended to speed up the performance of RSIM, but are provided only for purposes of comparison.