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- bpbtype
- Type of branch predictor included in the processor. The
argument is a string, and is specified as follows:
2bit | 2-bit history predictor [22]. This is the default. |
2bitagree | 2-bit agree predictor [24] |
static | static branch prediction using compiler hints
|
- bpbsize
- This number specifies the number of counters in the
branch prediction buffer (unused with static branch prediction). Defaults to 512.
- shadowmappers
- This number controls the number of shadow mappers provided for branch
prediction. Defaults to 8.
- rassize
- The number provided here sets the number of entries in the return address stack.
Defaults to 4.
- numalus
- This number specifies the number of ALU functional units in
the RSIM processor. Defaults to 2.
- numfpus
- This number specifies the number of FPU functional units in
the RSIM processor. Defaults to 2.
- numaddrs
- This number specifies the number of address generation units in
the RSIM processor. Defaults to 2.
- regwindows
- This number gives the number of register windows in
the RSIM processor (one of these is always reserved for the system). Must
be a power of 2 between 4 and 32, inclusive. Defaults to 8.
- maxstack
- This number specifies the maximum size of each simulated
process stack, in KB. Defaults to 1024.
The following pairs of parameters specify the
latencies and repeat delays of ALU and FPU instructions.
In each pair, the first element specifies the latency, while the second
specifies the repeat delay. The
latency is the number of cycles after instruction issue that the
calculated value can be used by other instructions. The repeat
delay is the number of cycles after the issue of an instruction
that the functional unit type used is able to accept a new instruction
(a value of 1 indicates fully-pipelined units). Each parameter below
is expected to be followed by a positive integer used to specify the
value of the corresponding parameter.
- latint,repint
- Latency and repeat delay for common ALU operations (e.g. add, subtract, move).
Default latency and repeat delay of 1 cycle.
- latmul,repmul
- Latency and repeat delay for integer multiply operations.
Default latency of 3 cycles and repeat delay of 1 cycle.
- latdiv,repdiv
- Latency and repeat delay for integer divide operations.
Default latency of 9 cycles and repeat delay of 1 cycle.
- latshift,repshift
- Latency and repeat delay for integer shift operations.
Default latency and repeat delay of 1 cycle.
- latflt,repflt
- Latency and repeat delay for common FP operations (e.g. add, subtract, multiply).
Default latency of 3 cycles and repeat delay of 1 cycle.
- latfmov,repfmov
- Latency and repeat delay for simple FP operations (e.g. move, negate, absolute value).
Default latency and repeat delay of 1 cycle.
- latfconv,repfconv
- Latency and repeat delay for FP conversions (e.g. int-fp, fp-int, float-double).
Default latency of 5 cycles and repeat delay of 2 cycle.
- latfdiv,repfdiv
- Latency and repeat delay for FP divide.
Default latency of 10 cycles and repeat delay of 6 cycle.
- latfsqrt,repfsqrt
- Latency and repeat delay for FP square-root.
Default latency of 10 cycles and repeat delay of 6 cycle.
Thus, to specify that common FPU operations have a latency of
5 cycles and a repeat delay of 2 cycles, the configuration file
should include:
Next: Cache hierarchy parameters
Up: Configuration file
Previous: Overall system parameters
Vijay Sadananda Pai
Thu Aug 7 14:18:56 CDT 1997