Alberto Ros

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I am Full Professor in the Computer Engineering Department at the University of Murcia, Spain. Funded by the Spanish government to conduct the PhD studies I received the PhD in computer science from the University of Murcia in 2009. I held postdoctoral positions at the Technical University of Valencia and at Uppsala University. I received an European Research Council (ERC) Consolidator Grant in 2018 to improve the performance of multicore architectures. Working on cache coherence, memory hierarchy designs, memory consistency, and processor microarchitecture, I have co-authored more than 100 peer-reviewed articles. I have been inducted into the ISCA Hall of Fame and MICRO Hall of Fame. I am IEEE Senior member.


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General

Prediction and Prefetching

Parallelism and hardware transactional memory

Security

Persistency

Processor design

Memory consistency and consistency-directed multicore coherence

Software-hardware co-design

Verification of cache coherence protocols

Argo: Distributed Shared Memory

Data and access classification

Separate private- and shared-data caches

List-based coherence protocols

Efficient caches

Coherence Deactivation

Shared distributed cache mapping policies

Extension of coherence protocols

Indirection-aware coherence protocols

Scalable directory caches

Coherence protocol evaluation

Simulation